As system-on-chip and multiple processor cores on a single chip are becoming common practice, simulating these complex chips is, in turn, becoming expensive and challenging. One of the techniques adopted in simulating these complex systems is Field Programmable Gate Array (FPGA) based hardware accelerators. These hardware accelerators work on the principle of dividing the chip design (device under test, referred to herein as “DUT”) into small blocks. These blocks are then implemented on various FPGAs. These FPGAs are inter-connected to each other in the same fashion as is the original DUT design. The chip or DUT simulations can now be run on this specialized FPGA hardware instead of running them on a conventional simulator. Conventional simulators are completely written in software and run on a general purpose computer. Hardware simulators can typically give a speed advantage of 100- to 1000-fold over conventional simulators.